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august 2010 doc id 14494 rev 5 1/20 20 l6392 high-voltage high and low side driver features high voltage rail up to 600 v dv/dt immunity 50 v/nsec in full temperature range driver current capability: ? 290 ma source ? 430 ma sink switching times 75/35 nsec rise/fall with 1 nf load 3.3 v, 5 v ttl/cmos inputs with hysteresis integrated bootstrap diode operational amplifier for advanced current sensing adjustable dead-time interlocking function compact and simplified layout bill of material reduction flexible, easy and fast design applications motor driver for home appliances, factory automation, industrial drives. hid ballasts, power supply units. description the l6392 is a high-voltage device manufactured with the bcd ?off-line? tech nology. it is a single chip half-bridge gate driver for n-channel power mosfet or igbt. the high side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos/ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp the ic embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control. dip-14 so-14 table 1. device summary order codes package packaging l6392n dip-14 tube l6392d so-14 tube l6392dtr so-14 tape and reel www.st.com
contents l6392 2/20 doc id 14494 rev 5 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 cboot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
l6392 block diagram doc id 14494 rev 5 3/20 1 block diagram figure 1. block diagram uv detection level shifter bootstrap driver s v cc lvg driver v cc hin lin hvg driver hvg out lvg boot uv detection op+ op- gnd opout sd dt opamp dead time r logic shoot through prevention floating structure + - v cc 3 2 13 14 7 5 6 1 4 12 8 10 9 from lvg 5v
pin connection l6392 4/20 doc id 14494 rev 5 2 pin connection figure 2. pins connection (top view) table 2. pin description pin n# pin name type function 1lin i low side driver logic input (active low) 2sd (1) i shut down logic input (active low) 3 hin i high side driver logic input (active high) 4 vcc p lower section supply voltage 5 dt i dead time setting 6 opout o opamp output 7 gnd p ground 8 op+ i opamp non inverting input 9 op- i opamp inverting input 10 lvg (1) 1. the circuit provides less than 1 v on the lv g and hvg pins (@ isink = 10 ma), with v cc > 3 v. this allows to omitting the ?bleeder? resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gat e driver assures low impedance also in sd condition. o low side driver output 11 nc not connected 12 out p high side (floating) common voltage 13 hvg (1) o high side driver output 14 boot p bootstrapped supply voltage vcc hin lin sd 1 3 2 4 nc out hvg boo t 14 13 gnd dt opout lvg op- 12 11 10 9 5 7 6 8 op+
l6392 truth table doc id 14494 rev 5 5/20 3 truth table note: x: don?t care table 3. truth table inputs outputs sd lin hin lvg hvg lxxl l hllhl hlhl l hhl l l hhh l h
electrical data l6392 6/20 doc id 14494 rev 5 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 12, 13 and 14 is guaranteed up to 1 kv (human body model) 4.2 thermal data table 4. absolute maximum rating symbol parameter value unit min max v cc supply voltage - 0.3 + 21 v v out output voltage v boot -21 v boot +0.3 v v boot bootstrap voltage - 0.3 620 v v hvg high side gate output voltage v out - 0.3 v boot + 0.3 v v ivg low side gate output voltage -0.3 v cc + 0.3 v v op+ opamp non-inverting input -0.3 v cc + 0.3 v v op- opamp inverting input -0.3 v cc + 0.3 v v i logic input voltage -0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t a = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 5. thermal data symbol parameter so-14 dip-14 unit r th(ja) thermal resistance junction to ambient 165 100 c/w
l6392 electrical data doc id 14494 rev 5 7/20 4.3 recommended operating conditions table 6. recommended operating conditions symbol pin parameter test condition min max unit v cc 4 supply voltage 12.5 20 v v bo (1) 1. v bo = v boot -v out 14-12 floating supply voltage 12.4 20 v v out 12 dc output voltage -9 (2) 2. lvg off. v cc = 12.5 v. logic is operational if v boot > 5 v. 580 v f sw switching frequency hvg, lvg load c l = 1nf 800 khz t j junction temperature -40 125 c
electrical characteristics l6392 8/20 doc id 14494 rev 5 5 electrical characteristics 5.1 ac operation table 7. ac operation electrical characteristics (v cc = 15 v; t j =+25 c) symbol pin parameter test condition min typ max unit t on 1 vs 10 3 vs 13 high/low side driver turn- on propagation delay v out = 0 v v boot = v cc c l = 1 nf v i = 0 to 3.3 v see figure 3 50 125 200 ns t off high/low side driver turn- off propagation delay 50 125 200 ns t sd 2 vs 10, 13 shut down to high/low side propagation delay 50 125 200 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 dead time setting range (1) r dt = 0; c l = 1 nf; c dt = 100 nf 0.1 0.18 0.25 s r dt = 37 k ;c l = 1 nf; c dt =100 nf 0.48 0.6 0.72 r dt = 136 k ;c l =1 nf; c dt =100 nf 1.35 1.6 1.85 r dt = 260 k ;c l =1 nf; c dt =100 nf 2.6 3.0 3.4 mdt matching dead time (2) r dt = 0 ; c l =1 nf; c dt =100 nf 80 ns r dt = 37 k ;c l =1 nf; c dt =100 nf 120 r dt = 136 k ;c l =1 nf; c dt =100 nf 250 r dt = 260 k ;c l =1 nf; c dt =100 nf 400 t r 10, 13 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 on page 9 2. mdt = | dt lh - dt hl | see figure 5 on page 13
l6392 electrical characteristics doc id 14494 rev 5 9/20 figure 3. timing characteristics figure 4. typical dead time vs. dt resistor value hin hvg 50% 10% 90% 50% t r t f t on t off 90% 10% lin lvg 50% 10% 90% 50% t r t f t on t off 90% 10% lvg/hvg sd 90% 50% t f t sd 10% 5gwn2kp '7xv ? $ssur[lpdwhgirupxodiru 5gwfdofxodwlrqw\s 5gw>n @ a'7>?v@
electrical characteristics l6392 10/20 doc id 14494 rev 5 5.2 dc operation table 8. dc operation electrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test condition min typ max unit low supply voltage section v cc_hys 4 v cc uv hysteresis 1200 1500 1800 mv v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; op + = gnd; op - = 5 v 120 150 a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; op + = gnd; op - = 5 v 680 1000 a bootstrapped supply voltage section (1) v bo_hys 14 v bo uv hysteresis 1200 1500 1800 mv v bo_thon v bo uv turn on threshold 10.6 11.5 12.4 v v bo_thoff v bo uv turn off threshold 9.1 10 10.9 v i qbou undervoltage v bo quiescent current v bo = 9 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; op + = gnd; op - = 5 v 70 110 a i qbo v bo quiescent current v bo = 15 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; op + = gnd; op - = 5 v 150 210 a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 a r ds(on) bootstrap driver on resistance (2) lvg on 120
l6392 electrical characteristics doc id 14494 rev 5 11/20 symbol pin parameter test condition min typ max unit driving buffers section i so 10, 13 high/low side source short circuit current v i = v ih (t p < 10 ms) 200 290 ma i si high/low side sink short circuit current v i = v il (t p < 10 ms) 250 430 ma logic inputs v il 1, 2, 3 low logic level voltage 0.8 v v ih high logic level voltage 2.25 v v il_s 1, 3 single input voltage lin and hin connected together and floating 0.8 v i hinh 3 hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i lini 1 lin logic ?0? input bias current lin = 0 v 3 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a i sdh 2 sd logic ?1? input bias current sd = 15 v 10 30 100 a i sdl sd logic ?0? input bias current sd = 0 v 1 a 1. v bo = v boot - v out 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 14 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 table 8. dc operation electrical characteristics (v cc = 15 v; t j = +25 c) (continued)
electrical characteristics l6392 12/20 doc id 14494 rev 5 table 9. opamp characteristics (v cc = 15 v, t j = +25 c) symbol pin parameter test condition min typ max unit v io 8, 9 input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (1) 100 200 na v icm input common mode voltage range 0v cc -4 v v ol 6 low level output voltage r l = 10 k to v cc 75 150 mv v oh high level output voltage r l = 10 k to gnd 14 14.7 v i o output short circuit current source, v id = + 1 v; v o = 0 v 16 30 ma sink v id = -1 v; v o = v cc 50 80 ma sr slew rate v i = 1 4; c l = 100 pf; unity gain 2.5 3.8 v/ s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k 70 85 db srv power supply rejection ratio vs v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the direction of input current is out of the ic.
l6392 waveforms definitions doc id 14494 rev 5 13/20 6 waveforms definitions figure 5. dead time - timing waveforms lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
typical application diagram l6392 14/20 doc id 14494 rev 5 7 typical application diagram figure 6. application diagram uv detection level shifter bootstrap driver s v cc lvg driver v cc hin lin hvg driver hvg h.v. to load out lvg boot cboot uv detection op+ op- gnd opout sd dt opamp dead time r logic shoot through prevention floating structure + - sd latch 3 2 13 14 7 5 6 1 4 12 8 10 9 from lvg 5v
l6392 bootstrap driver doc id 14494 rev 5 15/20 8 bootstrap driver a bootstrap circuitry is needed to supply the hi gh voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 7 a). in the l6392 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with diode in series, as shown in figure 7 b. an internal charge pump ( figure 7 b) provides the dmos driving voltage. 8.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: c boot >>> c ext e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage and quiescent losses. e.g.: hvg steady state consumption is lower than 200 a, so if hvg t on is 5 ms, c boot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1 v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ). at low frequency this drop can be neglected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. c ext q gate v gate ------------- - = v drop i ch e arg r dson v drop q gate t ch e arg ------------------ r dson ==
bootstrap driver l6392 16/20 doc id 14494 rev 5 for example: using a power mos with a total gate charge of 30 nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 7. bootstrap driver v drop 30nc 5 s -------------- - 120 0.7v ? = to load d99in1067 h.v. hvg ab lvg hvg lvg c boot to loa d h.v. c boot d boot boot v s v s v out boot v out
l6392 package mechanical data doc id 14494 rev 5 17/20 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. dip-14 mechanical data and package dimensions dip14 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100 outline and mechanical data
package mechanical data l6392 18/20 doc id 14494 rev 5 figure 9. so-14 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.30 0.004 0.012 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 8.55 8.75 0.337 0.344 e 3.80 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so14 0016019 d
l6392 revision history doc id 14494 rev 5 19/20 10 revision history table 10. document revision history date revision changes 29-feb-2008 1 initial release 18-mar-2008 2 cover page updated 17-sep-2008 3 updated table 4 on page 6 , table 4 on page 6 , table 9 on page 12 17-feb-2009 4 updated table 7 on page 8 , table 8 on page 10 , table 9 on page 12 added table 4 on page 9 11-aug-2010 5 updated cover page, table 1 on page 1 , table 7 on page 8 , ta b l e 9 on page 12
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